Please use this identifier to cite or link to this item:
|Title:||ALL MOS low-power low-voltage LDO with an embedded voltage reference||Authors:||Chandra, Bernardus Edwin||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2018||Abstract:||The Low Drop-out Voltage (LDO) regulators are widely used in present electronic industry. Such voltage regulator is one of the subsystems in the power management unit. This LDO consumes very little current and will be designed in a 0.18µm CMOS technology. The minimum unregulated input voltage, Vin, is typically 1.2 voltage, and the output voltage is an unscaled temperature compensated voltage in a voltage-mode approach derived from summing the PTAT and CTAT components, generated from transistors operating in the sub-threshold region of operation. This report presents 2 designs of Low Dropout (LDO) Voltage Regulator. The first design consists of a start-up circuit, error amplifier (EA) with embedded voltage reference. The second design is the modification of the first design with addition of curvature correction circuit to reduce the temperature coefficient. All the simulations are done in Cadence Virtuoso Environment using 0.18µm Global Foundries technology node. The proposed design can supply the voltage of 677 mV with minimum supply voltage of ~690 mV. The second design provides excellent temperature coefficient (TC) of 4.39 ppm/oC ranging from -40oC to 120oC. The LDO can regulate load current of 36mA. The line regulation obtained is 16.74 mV/V and the load regulation is 0.284 mV/mA. Lastly, improvements and drawback of the design are summarized at the very end of the report.||URI:||http://hdl.handle.net/10356/75350||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.