Please use this identifier to cite or link to this item:
Title: Resistor-less low dropout voltage regulator
Authors: Lee, Han Jian
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2018
Abstract: A Low Dropout Voltage Regulator (LDOVR) for memory circuits in the R-WSNs for biomedical devices is presented in the following report, providing a stable output voltage of 0.9V that is almost independent towards temperature, load variations and input supply voltage of 1.2V. The LDOVRs proposed mainly consists of an EA with an embedded Voltage Reference and an output stage that consist of a power transistor. The report proposes two main design, a LDOVR using a self-cascode structure at the output and a Resistor-less LDOVR. The two designs are implemented and simulated in a licensed Cadence Virtuoso environment using the 0.18μm Global Foundries Technology process. The first design can achieve good line regulation and load regulation with a decent load range. However, it was unable to have a stable overall performance at an output voltage of 0.9V. Hence, the challenge was to have a higher output voltage and to design a resistor-less LDOVR (R-LDOVR) at the same time. The second design is the final design of this report, an R-LDOVR. It has an output voltage of 0.9V with an input supply voltage of 1.2V. The design has a TC of 9.87℃ ( -40℃ to 140℃ ), line regulations of 25mV/V and a load regulation of 0.00156 mV/mA. It only consumes a quiescent current of 17.5μA. The design has a good stability performance of 96° phase margin with no load and 89° phase margin with full load. Problems Encountered along the way are mentioned with solutions overcoming them. The report ends of with suggestions to enhance and improve the current design for future efforts. First possible improvement is introducing a more stable resistor-less voltage reference in terms of the effect of the change in voltage supply. This would allow the design to have a better line regulation. Moreover, suggestions were made to enhance the circuit with the output capacitorless method which allows the design to have better transient response without an off-chip capacitor.
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
FYP Lee Han Jian.pdf
  Restricted Access
Final Report8.17 MBAdobe PDFView/Open

Page view(s) 20

checked on Sep 25, 2020

Download(s) 20

checked on Sep 25, 2020

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.