Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/75677
Title: Low-voltage aging-tolerant sram designs
Authors: Lee, Zhao Chuan
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2018
Source: Lee, Z. C. (2018). Low-voltage aging-tolerant sram designs. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: The sub-threshold or near-threshold operation has been an attractive option for digital integrated circuit design due to the explosive growth of battery operated devices. This approach utilizes ultra-low/low supply voltage to decrease switching energy and suppressing leakage current to achieve low power operation. The effectiveness of power reduction makes it an excellent approach to prolong the battery lifetime and create an alternative opportunity for healthcare monitoring devices, which have limited power budget and low to medium signal processing capability. Static Random Access Memory (SRAM) is known as the critical building block in digital very large-scale integration (VLSI) circuit. It consumes large area overhead with high integration density in the modern System on Chip (SoC). This causes a large amount of leakage power contributed from SRAM array and is recognized as one of the bottlenecks in sub-100nm technologies. Therefore, application-specifically designed SRAMs for low power signal processing SoC have been popular and necessary. A column based split cell-VSS (CS-CVSS) data-aware write-assisted 9T SRAM with enhanced read sensing margin is developed. The CS-CVSS data-aware write assist improve both half-selected static noise margin and write margin while a 3T read port structure is applied for read sensing margin improvement. A 16kb 9T SRAM test chip with the proposed techniques is fabricated in 28-nm fully depleted silicon on insulator (FDSOI) technology and demonstrated VDD, MIN-Write = 470mV and VDD, MIN-Read = 250mV. Apart from suffering large leakage power consumption, SRAM reliability is another limiting factor in sub-100nm technology due to temporal variations. Temporal variations such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) shift the device threshold voltage (Vth) over its functional periods and eventually lead to soft or hard failures. In particular, BTI has been recognized as the most critical and challenging temporal variation that limits the lifetime of SRAMs much worse than HCI. The critical SRAM operation margins include minimum operating voltage, Vmin, cell stability and read/write stability. To circumvent the BTI aging in SRAMs, a dynamic reliability management that consists of BTI-Aware Stability Monitor (BTI-SM) assisted with Two-Phase Write Operation (TPWO) is proposed. The BTI-SM monitors the BTI degradation in SRAM cells through a replica row and adjusts the WWL voltage level with the assist of TPWO. The TPWO divides the write wordline (WWL) voltage level into two phases to improve the degraded half-selected cell stability due to BTI degradation without compromising other circuit parameters. Test chip measurement shows that the half-selected cell stability failure is reduced significantly from 57.13% down to 0% with the proposed techniques at a 10% area and 3.42% power overheads in 28-nm FDSOI 16kb SRAM.
URI: http://hdl.handle.net/10356/75677
DOI: 10.32657/10356/75677
Schools: School of Electrical and Electronic Engineering 
Research Centres: Centre for Integrated Circuits and Systems 
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

Files in This Item:
File Description SizeFormat 
Thesis_May_31.pdf7.24 MBAdobe PDFThumbnail
View/Open

Page view(s)

408
Updated on Jun 23, 2024

Download(s) 50

163
Updated on Jun 23, 2024

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.