Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/75715
Title: Human machine interface/brain control for electric vehicles application
Authors: Tang, Tao
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2018
Publisher: Nanyang Technological University
Source: Tang, T. (2018). Human machine interface/brain control for electric vehicles application. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Human machine interface (HMI) that provides easy-to-use and effective interaction between human and Electric Vehicles (EV) has attracted remarkable research interests. Various HMI approaches have been reported to improve the driving experience and enhance safety. Among different potential candidates, Electroencephalogram (EEG) is a promising approach by recording brain signals with the electrodes on the scalp and decoding the signaling with real-time brain signal processing. Since body movement is not required to generate the signaling, risks of distraction to the driver is minimized. Multi-channel analog front-end (AFE) is a key building block in HMI for EV applications. This work describes the design of four AFE for wearable HMI in EV applications. Firstly, a 4-channel TDM-based EEG AFE is presented which focuses on the improvement of Common Mode Rejection Ratio (CMRR). A system-level innovation of combining chopping stabilization (CS) and time division multiplexing (TDM) is proposed to achieve a system-level CMRR enhancement. Secondly, the same design methodology is extended to a 16-channel TDM/CS AFE with tunable DC-servo loop and fine-trimming input impedance boosting loop. A 4-bit calibrated impedance boosting loop contributed to the input impedance of 560 MΩ as well as CMRR for input interface. A tunable DC-servo loop (TDSL) is designed to cancel the maximum input DC offset of 200 mV at a controlled speed so that the TDSL achieves a fast cancellation for the input DC offset without any glitch injection. Thirdly, a novel area-efficient driven-right leg (DRL) circuit is proposed for multi-channel neural recording AFE. A capacitor-free DRL structure is proposed which provides 60 dB enhancement of system-level CMRR with 90% area reduction for the DRL circuit. Finally, a low-power, low-noise bio-potential recording AFE is developed with enhanced power efficiency factor (PEF) performance. The AFE has obtained the smallest PEF under ultra-low power supply of 0.5 V with power consumption of 2 µW and a low input-referred noise of 2.1 µVrms that is achieved by high-frequency chopping scheme.
URI: http://hdl.handle.net/10356/75715
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
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