Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/76073
Title: Module level verification for low Power SoC based on universal verification methodology
Authors: Zhang, Zijing
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2018
Abstract: The thesis pertains to study the specification of the low power mix-signal SoC and develop a well-rounded verification environment and testcases using the Universal Verification methodology (UVM) for one module, Pulse Density Modulation(PDM). The verification task includes building up verification plan, establishing verification components, designing and developing testcases. The module level verification environment is expected to be portable from projects to projects. The Device Under Test (DUT) is a module inside one low power mix-signal SoC platform contains analog modules and subsystem with ARM Cortex-M family core. PDM module is widely used in microphone and sigma-delta modulated sensor application. A PDM bitstream is encoded from an analog signal through the process of delta-sigma modulation. The relative density of pulses corresponds to the analog signal’s amplitude. Verification method, testcases and results analysis have been introduced in this thesis, including critical algorithm and data process details. After the verification fully implemented, an expected target of simulation result and coverage have been achieved.
URI: http://hdl.handle.net/10356/76073
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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