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|Title:||FPGA implementation of Kahan summation algorithm||Authors:||Darshni, R||Keywords:||DRNTU::Engineering::Computer science and engineering||Issue Date:||2018||Abstract:||In this project, Kahan Summation Algorithm, and an improved version of it, Kahan- Babuska Algorithm have been implemented in an FPGA platform to increase the accuracy in basic floating-point computation The Kahan Summation Algorithm is a method to add floating point numbers in a way to reduce the accumulation of error. The designs are configurable to sum to 100 floating point numbers. There are two implementations of the Kahan Summation Algorithm design, a purely blocking mode, and a hybrid mode with pipelining. The Kahan-Babuska algorithm is implemented in blocking mode. The designs have also been compared with each other, along with software implementations to study the effectiveness of the implementation.||URI:||http://hdl.handle.net/10356/76134||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SCSE Student Reports (FYP/IA/PA/PI)|
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