A high speed 16-bit CMOS multiplier IC design

Abstract

In this project, various multiplication algorithms are investigated and used to implement 16-bit CMOS multiplier design. And some common adders are also studied and developed using Verilog HDL language. By using different combination of algorithm and adder, we will study the performance of each 16- bit multiplier design. Vedic algorithm, Wallace tree algorithm and booth algorithm are proposed in the project to implement 16-bit multiplication. Functional model of all the 16-bit multiplier design were developed using Verilog HDL language. The simulation using Verilog Complier was shown to have successful multiplication function. And schematic was synthesized on Design Vision in AMS 0.36um technology.