Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/76261
Title: A high speed 16-bit CMOS multiplier IC design
Authors: Chen, Yin
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2018
Abstract: In this project, various multiplication algorithms are investigated and used to implement 16-bit CMOS multiplier design. And some common adders are also studied and developed using Verilog HDL language. By using different combination of algorithm and adder, we will study the performance of each 16- bit multiplier design. Vedic algorithm, Wallace tree algorithm and booth algorithm are proposed in the project to implement 16-bit multiplication. Functional model of all the 16-bit multiplier design were developed using Verilog HDL language. The simulation using Verilog Complier was shown to have successful multiplication function. And schematic was synthesized on Design Vision in AMS 0.36um technology.
URI: http://hdl.handle.net/10356/76261
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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