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Title: Design of a 40nm CMOS operational amplifier for high resolution LCD drver applications
Authors: Swasthika, Saravanan
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2018
Abstract: In this work, an improved Cross Feedforward Cascode Compensation (CFCC) amplifier with Slew Rate Enhancement (SRE) circuit, which is suitable for LCD Driver application, has been presented. Implemented with TSMC 40nm CMOS technology, the presented CFCC amplifier is capable of operating at high capacitive load from 150pF to 15nF. The reported Complementary Based Cross Coupled (CBCC) Operational Transconductance Amplifier (OTA) technique and 3-step Nested Current Mirror (NCM) Operational Transconductance Amplifier (OTA) are discussed. They are employed to serve as benchmark topologies. The performance comparison has focused on the parameters such as DC gain, phase margin (PM), gain margin (GM), unity-gain frequency (UGF), slew rate (SR) and settling time with capacitive load of 150pF, 500pF and 15nF at similar power consumption. This simulation results have shown that the improved amplifier can maintain stability across the capacitive load range whilst offering better DC gain, UGF, SR and settling time. Besides, the improved amplifier displays 25% improvement in the settling time at the maximum of capacitive load of 15nF when compared with the same amplifier without SRE circuit. This has validated that the proposed SRE circuit will be useful for particular heavy capacitive load. Finally, the corner simulation results pertaining to PM, UGF and GM are conducted, demonstrating that the amplifier can sustain the performance under process and temperature variations. As a result, this has confirmed the effectiveness and robustness of the amplifier for use as the high resolution LCD driver.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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