Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/76869
Title: Trimming and calibration in RF receiver chain
Authors: Pillai, Shylaja Shruti
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Antennas, wave guides, microwaves, radar, radio
Issue Date: 2019
Abstract: The focus of this dissertation is to investigate on know how to trim and calibrate Global Navigation Satellite Systems (GNSS) receiver chain of a cellular phone for efficient characterisation. Trimming and calibration is performed on Phase-Locked Loop (PLL), Analog to Digital converter (ADC), Local Oscillator (LO) and Low-Dropout (LDO) Voltage Regulator blocks in the receiver chain. Additionally, resistors and capacitors are also trimmed to improve the performance of the Trans Impedance Amplifier (TIA). A detailed study is carried out in literature survey to explore the existing methods to trim and calibrate the above-mentioned blocks and components in the Radio Frequency (RF) receiver chain. Phase-Locked Loop (PLL) and Analog to Digital Converter (ADC) calibration is done in an automatic manner by using digital trim techniques and auto calibration units upon board power on. Resistor, Local Oscillator (LO) and Low-Dropout (LDO) Voltage Regulator calibration are done manually by enabling and writing the corresponding trim registers installed in the chip after board power on. With technology scaling, design of analog devices has become more complex as it depends on balancing many parameters. Post-production performance calibration is used to balance the parameters. Tuning knobs are added across various blocks in an analog circuit at the design stage to mitigate variations after production. Tests are carried out in Automatic Test Equipment to quantify variations in the performance specifications and these variations are fused in to a non-volatile memory embedded in the chip. The applications of these variations during bench validation is called trimming and calibration. The bench validation process starts with trimming and calibration before actual validation is carried out to achieve improved accuracy. Once the chips arrive from production, they are powered on to read the trim codes from the memory. This procedure is carried out across Typical, Fast and Slow corners. Once the trim codes are read the best code is selected for optimised performance for every design block. In this dissertation I will be discussing the trimming and calibration procedure for Resistor, Capacitor, Phase-Locked loop (PLL), Local Oscillator (LO), Low-Dropout (LDO) and Voltage Regulators.
URI: http://hdl.handle.net/10356/76869
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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