Design and verification of a fast low-dropout regulator for a high performance receiver chain targeting GNSS applications

Abstract

Low-dropout (LDO) voltage regulators are arguably the most popular designs used in integrated circuit (IC) power management. In this project, we aim at designing a LDO regulator with a fast load transient response suitable for supplying power to one of the blocks present in a Global Navigation Satellite System (GNSS) receiver chain. A GNSS receiver, such as a Global Positioning System (GPS) receiver chain consists of multiple cascaded blocks, where each one contributes to the down conversion process of the feeble GPS signals received from a satellite in space. The design specification of the LDO regulator is obtained from the load, which in this case is a time-to-digital (TDC) convertor operating at a high frequency. TDCs are used as counters or for purposes of time-keeping in the synthesizer block of the receiver chain. This thesis work presents the fast-LDO regulator needed to power the aforementioned block, while also providing the procedure followed to carry out the design. The design is then tested for DC analysis, stability analysis, load transient response, line transient response, load and line regulation and power supply ripple rejection. The performance of the voltage regulator is measured by conducting schematic simulations in Cadence Virtuoso Analog Design Environment and verified against the theoretical design calculations.