Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/77468
Title: Timing mismatch calibration for time- interleaved ADC
Authors: Tan, Clarice Wen Ying
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2019
Abstract: The project displays an all-digital background calibration for timing mismatch in time-interleaved analog-to-digital converter. Digital adaptive timing mismatch estimation and digital derivative based correction is combined to attain lower cost and better correction of timing mismatch. An expression for signal to noise and distortion ratio (SNDR) of four-channel after correction. Simulation result will show signal of various stages of the project (sampling by each ADC channels, the signal after derivative filter, timing mismatch estimator, and corrected signal). Results also confirm SNDR characteristic of vin, sampled and corrected signals.
URI: http://hdl.handle.net/10356/77468
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
official FYP report.pdf
  Restricted Access
4.07 MBAdobe PDFView/Open

Page view(s)

205
Updated on Jun 13, 2024

Download(s)

10
Updated on Jun 13, 2024

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.