Ultra-low power CMOS circuit for IoT

Abstract

Nowadays, the research interest of the ultra-low power (ULP) designs in any IoT devices or systems has become popular and most needed since the increased in the power consumption of the Integrated circuits (ICs) are affecting the battery lifespan of the IoT systems or devices. In this project, various CMOS power reduction techniques have been studied and used to come out with a few proposed full adder designs based on the arithmetic logic unit (ALU) of an IoT sub-system. Furthermore, the few proposed full adder topologies will go through simulations under the 40nm Cadence Virtuoso software based on nominal voltage supply of 1V to be scaled down to 0.45V or as low as possible till the output signal gets degraded. Based on simulation results, the proposed 6T full adder design has the most reduction in power dissipation, transistor counts as well as the best power delay product (PDP) among the other full adder circuits. Thus, the proposed 6T full adder design could further be used as standard cell in building up more N-bits full adder or a multiplier that will be recommended in future for the system architecture level of design.