Low voltage low power CMOS circuits for IoT applications

Abstract

The internet of things (IoT) technology, growing at an unprecedented rate, has huge impact on our lives and the industries. The prevalence of IoT also hints severe security risk if any successful attack against the IoT device is launched. At the same time, IoT devices, being mostly battery powered, are designed to operate at low voltages and have extremely low power consumption to prolong its battery life. With the hardware constraints of IoT devices, computing power at each node is low, limiting the devices from having computation heavy security measures. Currently, IoT devices use non-volatile memory (NVM), such as Erasable Programmable Read Only Memories to store secret keys. However, this approach not only takes up extra chip area, and also opens gateway for possible physical attacks on the chip to retrieve the secret keys. Innovative solutions like physically unclonable function (PUF) have been proposed to enhance security features of devices. PUF based on static random-access memory (SRAM) are superior in terms of randomness, bit-aliasing and uniformity. Dual mode SRAM PUF, capable of both memory and PUF operation, also reduces the need for extra circuitry for generating PUF response. In this report, the behaviour of SRAM cell at low voltages is analysed for memory mode and PUF mode using simulation result from Cadence with TSMC 40nm technology to design SRAM cells optimised for both modes. 3 designs, including 1 new SRAM cell structure, for dual-mode SRAM PUF cells are developed, one for operation at 600mV and the other two for operation at 450mV.