Please use this identifier to cite or link to this item:
|Title:||Low power convolutional neural network (CNN)||Authors:||Lim, Wu Cong||Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2019||Abstract:||Artificial intelligence (AI) is the cutting-edge technology at this information age. However, the computational cost of AI relevant application is very expensive. Thus, the power consumption of AI application is too high to be implemented on a mobile device. The development of the algorithm for AI application is advancing at a very fast speed; it is very difficult for the development of the hardware counterpart to catch up with the development in the algorithm. A middle way for the hardware development to catch up with the algorithm development is to design the hardware from a semi-custom approach such as Field Programmable Gate Array (FPGA). The semi-custom approach allows the designer to design customized hardware for a specific function or algorithm. This project presents a design of hardware implemented Convolutional Neural Network with FPGA evaluation board, Xilinx Zedboard. Different design methodologies are being used to evaluate the design performance such as power efficiency, speed performance, and utilization of LUT in FPGA. The project comprised of knowledge that relevant to software programming of Convolutional Neural Network, and hardware programming and simulation did with VHDL. A model for recognizing the handwritten digits is trained and being implemented on the design.||URI:||http://hdl.handle.net/10356/77771||Rights:||Nanyang Technological University||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
Files in This Item:
|3.36 MB||Adobe PDF||View/Open|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.