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dc.contributor.authorWong, Ken Khooi Lam
dc.description.abstractThis report pertains to design a digital pulse width modulator (DPWM) which can function at least 100MHz and has circuits of smaller area. The work is done to explore the differences of the structure of various types of DPWM, which are counter – based DPWM, tapped delay line (TDL) DPWM and hybrid DPWM, and target for the design of DPWM which has circuits of smaller area and can be able to function in various range of frequencies in the future. Cadence Virtuoso will be used to draw circuit diagram. ARM library which consists of most elements such as AND gate, OR gate, NOT gate, etc, will be deployed to design the DPWM. Various parts of subcircuits need to be designed such as a 100MHz-current-starved ring oscillator, 400MHz-current-starved ring oscillator, a delay chain, a 16-to-1 multiplexer (MUX), a bits justification block, and three output blocks. The process technology is 180nm CMOS, the supply voltage applied is 1.8V and the maximum simulation time is 40ns. Three types of modified TDL DPWM have been proposed and compared, which are double – resetting TDL DPWM, low power TDL DPWM and high accuracy TDL DPWM. The DPWM outputs could be produced during rising edges and falling edges of the delayed 100MHz oscillation signal in all three types of modified TDL DPWM. A 16-to-1 MUX is applied instead of using 32-to-1 MUX and the number of delay elements and buffers in the delay chain has been reduced from 32 to 21. From the simulation results, double resetting TDL DPWM dissipates the highest power meanwhile low power TDL DPWM dissipates the lowest power which is around 42.4% of the dissipated power of double resetting TDL DPWM. However, the difference between ideal pulse width and measured pulse width for each input is significant and the standard deviation of time gap of low power are the highest. For high accuracy TDL DPWM, the difference between ideal pulse width and measured pulse width for each input is very small and the standard deviation of time gap of low power are the lowest.en_US
dc.format.extent136 p.en_US
dc.rightsNanyang Technological University
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.titlePower management circuit for smart dusten_US
dc.typeFinal Year Project (FYP)en_US
dc.contributor.supervisorGwee Bah Hweeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeBachelor of Engineering (Electrical and Electronic Engineering)en_US
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Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)
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