Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/78162
Title: Frequency compensation in an input folded-cascode output buffered opamp with high PSRR
Authors: Angtoni, Erik
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2019
Abstract: Low power low voltage systems are important aspect in every portable device. Powering up a device using a low voltage supply limits the maximum and minimum input voltage. To fully utilise a device with low voltage, the input voltage should be allowed to be as close as possible to the supply voltage. This project presents op-amp design that enable rail-to-rail input and output stage. PMOS and NMOS differential pair are utilised as the input stage to achieve a rail-to-rail input stage. However, there exists a region where both transistors are on and causes gm to be nonconstant. Overlapping transition region technique is implemented to achieve a constant gm at the input stage. The designed circuit allows rail-to-rail input and output voltage with input stage gm variation of 5%-6%. Open-loop gain of 89.67dB and phase margin of 61.24° are achieved. Total Harmonic Distortion at fundamental frequency of 1kHz allows input voltage of 0.83Vpp at 0.01% or -80dB. CSM 0.18μm process technology is used in Cadence Custom IC Design Tools (Virtuoso Front to Back Design Environment) to complete this project.
URI: http://hdl.handle.net/10356/78162
Schools: School of Electrical and Electronic Engineering 
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
FYP A2181-181.pdf
  Restricted Access
3.77 MBAdobe PDFView/Open

Page view(s)

238
Updated on Jul 13, 2024

Download(s) 50

26
Updated on Jul 13, 2024

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.