Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/78207
Title: Design and analysis of low-power and high-speed Manchester carry-bypass adders
Authors: Fu, Yunyun
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2019
Abstract: This project pays more attention to low power Manchester carry-bypass adders. compared with the ripple carry adder and Carry-select adder, power consumption of Manchester adder under 1V supply voltage are improved by 47.1% and 36.97% respectively. Two ways of improving Manchester adder performance are proposed . Reducing Vdd is a good way to reduce power consumption as long as the circuit speed meets requirement. When the supply voltage drops from 1.2V to 0.8V, the power consumption is reduced by 58.73%. Using double carry chain is the other effective way. For 8-bit Manchester adder , double carry chain structure have 55.64% less worst case delay time than conventional Manchester carry-bypass structure under the condition of 1V supply voltage, however, the power consumption of double carry chain is higher than conventional Manchester adder. All the simulations were done in Cadence environment using TSMC 40nm CMOS technology.
URI: http://hdl.handle.net/10356/78207
Rights: Nanyang Technological University
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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