Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/78231
Title: Low power high performance CMOS adder design
Authors: Wen, Han
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2019
Abstract: The 20th century is an era of rapid development of IC. The rapid development of information industry such as computers has promoted the integrated circuit industry. IC electronic devices have also attracted more and more attention. Most very VLSI have a wide range of applications in daily life, such as cpu, gpu, and a huge range of processors, which use many mathematical operations. In those wide-spread used products, subtraction and multiplication are used more, and adders are the basic unit that makes up these operations. Therefore, improving the performance of the adder plays a key role in improving the overall module. At the same time, with the widely use of IC products such as cellphones and handheld computers, IC design engineers have to further enhance the performance of the computing modules, especially size of the circuit the and the power consumption. Adder is the basic component of arithmetic operation in microprocessor. When performing arithmetic operations on various microprocessors, DSP devices and digital circuits, the most basic circuit is often a binary adder. As for subtraction, it can be supplemented by means of compensation. The addition of the code is implemented, the multiplication is equal to the continuous addition, the division is a continuous subtraction, and the comparison operation can also be implemented by subtraction. The importance of high-speed, compact, low-power, high-performance adders in microprocessor systems is evident. This dissertation proposes four new low power adder units. The Cadence simulation results in the TSMC 40nm process show that the adder units of the four new structures have their own advantages in power dissipation, speed and power-delay product respectively. But they all meet the design requirements of low power consumption. Finally, this dissertation also proposes a 8-bit dynamic high-speed low-power adder. The simulation results also show that this adder can achieve high-speed and low-power design goals.
URI: http://hdl.handle.net/10356/78231
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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