Ultra-low power 8-bit CMOS adder design based on approximate arithmetic

Abstract

In response to the Moore's law and fast-pace society, low power and high speed IC design has become one of the most critical issues in semiconductor industry. Full adder is a commonly-used calculation tool in reality so that it can be a typical sample for low power IC design. In this paper, 1-bit conventional precise CMOS full adders and novel CMOS full adders based on approximate arithmetic are proposed to built the calculation unit for the adder chain. Several different 8-bit CMOS adder chains containing different numbers of approximate full adders at the LSB (Least Significant Bit) are proposed following. Simulation results of all the input and output signals will be plotted in the form of waveform. The total power consumption, the delay time variation curve and the average delay time of different proposed full adders will also be tested in the paper with Cadence Virtuoso software. Results will be tabled, compared and analyzed in the conclusion part. In addition, the circuits in this paper use the advanced technology of TSMC 40nm at the transistor level in IC design flow.