Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/78481
Title: Low power CMOS adiabatic logic design
Authors: Peng, Yuhang
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2019
Abstract: Low power technology has been considered increasingly significant because of the popularization of portable electronic products. Adiabatic switching technology, as a promising branch of the low power filed, can save power greatly by altering the circuit topologies. In this dissertation, basic principles of adiabatic switching are introduced, and basic circuits, including inverters, AND gates, XOR gates and so on, are simulated and compared using three different adiabatic structures (Efficient Charge Recovery Logic, Complementary Energy Path Adiabatic Logic and Clocked Adiabatic Logic). The focuses of the dissertation are the design of 4-bit full adders based on ripple-carry structure and 4-bit multipliers based on Wallace Tree structure using adiabatic logic families. All the power consumptions of these circuits are tested in Cadence Virtuoso software using TSMC’s 40nm technology and compared at different frequencies and voltages.
URI: http://hdl.handle.net/10356/78481
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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