Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/78498
Title: Low power design for SRAM
Authors: Chen, Jiahuan
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2019
Abstract: As the development of microelectronics technology, the design of memory cell has already become an important embranchment in today’s semiconductor design. Memory cell presents a development trend towards more integration, more speediness and more low-power along with the size shrink of semiconductor process. 80% of the wafer area in digital design is used for memory chips, and the percentage of SRAM in kinds of memories also increases. SRAM nowadays plays an important role in semiconductor memories. It has a wide application in high-speed data-exchange systems, like computer, communications, multimedia etc. Therefore it has a far-reaching signification to have a deep study in SRAM. What’s more, SRAM has already gained a driving development because of its characteristics of low power consumption and high operation speed. At the same time, many kinds of system chip embedded by SRAM also experience rapid development. As a result, the studies of lower power SRAM design have become a hotspot in today’s integrated circuit design. This dissertation mainly discusses how to optimize SRAM structure from the aspect of design, and makes comparisons of different kinds of design to select the best one for a certain SRAM circuit. In this dissertation, the first chapter starts by introducing the background of memory cells and some main memory cells in today’s SRAM circuits, as well as the basic structure of these cells. Chapter 2 analyzes the performance of traditional memory cell structure, like 4-transistor SRAM, 6-transistor SRAM, 10-transistor P-P-N SRAM. In this chapter, the differences and advantages of each structure are discussed, as well as the working principle of traditional 6-transistor SRAM. The third chapter takes these three SRAM structure as examples, discusses how to achieve low power by calculating the delay, waveform and power consumption of each structure. This chapter also briefly introduces other methods for low power design, like pulse signal technique, divided bit line and word line techniques. All of these techniques are widely used in today’s design and manufacture. Chapter 4 mainly discusses a three-inverter ring oscillator and its performance through Cadance. This dissertation not only compares the power consumption of each design, but also calculates other parameters like time delay and frequency that also play an important role in IC design.
URI: http://hdl.handle.net/10356/78498
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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