Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/78797
Title: Improvement of micro-strip GaN-on-SiC backside via-holes process
Authors: Yu, Zhuoran
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2019
Abstract: When people think of power electronics applications for wide-bandgap semiconductor materials, they often consider silicon carbide or gallium nitride. This is not surprising, as silicon carbide and gallium nitride are the wideband gap semiconductors used in the world's most advanced power electronics applications. However, for the fabrication of Micro-strip SiC HEMT, the interconnection of the source part is always a critical problem. Fortunately, Via-hole processes for the backside of SiC substrate is a proved method which can ground source region together under the bottom, Therefore, It can improve the performance of Microwave transmission and save the design space for the other interconnections. From this project, you would understand how this interconnection was fabricated in the clean room by a few processes like Lapping for SiC material, CMP for smooth and uniform surface, Ni plating for the hard mask, SiC dry etching for Via-hole. Other than that, there are also a few continuous improvements for the above processes. My project will mainly concentrate on the fabrication of the SiC lapping and Via-hold dry etching. Specific details for each step will be introduced in the following chapters.
URI: http://hdl.handle.net/10356/78797
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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