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dc.contributor.authorRadhakrishnan, Sathiya Priyanka
dc.description.abstractThis dissertation aims in studying and analysing of lower power high-speed CMOS circuit for which full adder of different topologies are constructed to finally cascade it to form 4:2 and 8:2 CMOS data compressor. Compressors are the main building bock of an ALU which finds in own application in multipliers, encoder, shifters, and all the digital signal processing units which is a major component of a CPU. In this dissertation, different topologies of same one bit full adder performance is analysed in terms of total power consumption which includes static and dynamic power consumption, total delay which is the average of rise time and fall time delay and power delay product in the supply voltage range of 900mV to 1.1V and frequency range of 250 MHz to 1 GHz, as the specified standard operating voltage by TSMC for 40 nm node technology is 1.1 V. By analysing different topologies, the best performing full adder is considered in terms of total power consumption, total delay, number of transistors and power delay product to construct 4:2 and 8:2 compressor to evaluate and study their performance characteristic. These schematic simulations are done in Cadence Virtuoso software with TSMC 40nm technology library and the results are studied and concluded saying transmission gate, dynamic logic and 10T XOR gates show better results among all in which transmission gate logic showed good performance results used to construct 4:2 and 8:2 CMOS data compressor.en_US
dc.format.extent80 p.en_US
dc.subjectEngineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.titleHigh speed low power CMOS data compressor design and analysisen_US
dc.contributor.supervisorLau Kim Teenen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeMaster of Science (Electronics)en_US
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Updated on Jun 23, 2021


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