Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/78918
Title: Design of Low Power Arithmetic Logic Unit
Authors: Senthilvel, Vignesh
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2019
Abstract: ALU is one of the core components of the central processing unit (CPU) of a computer. An arithmetic logic unit (ALU) is a combinational digital electronic circuit that performs various arithmetic operations like Addition (with carry), Increment, Subtraction (with borrow), Decrement, Two’s Complement, Multiplication, etc. and various logical operations like Bitwise AND, OR, XOR etc. and shift operations such as Arithmetic shift and Logical shift. Each of these functionalities represents individual modules within an ALU. The power consumed by all these modules is the total power consumption of an ALU. When the complexity of the modules increases, ALU could take up more space in the CPU, consume more power and dissipates energy in the form of heat. This dissertation focuses on Low power ALU design without compromising its performance. Reducing the power consumption of an ALU means reducing the power consumption of individual modules. All the modules are made up of logic gates. Using low power consuming logic gates would bring down the power consumption of all modules. As Phase-I of this dissertation, low power consuming logic gates would be constructed using various existing logic styles, techniques, and devices and compared to the standard version. Phase-2 involves designing the modules using low power logic gates and optimizing the modules to a possible extent. All the circuits constructed in this work use (MOSFET) TSMC 40nm technology and simulations are done using the Cadence Virtuoso software tool.
URI: http://hdl.handle.net/10356/78918
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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