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|Title:||An area- and power-efficient FIFO with error-reduced data compression for image/video processing||Authors:||Zeinolabedin, Seyed Mohammad Ali
Kim, Tony T.
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic systems||Issue Date:||2014||Source:||Zeinolabedin, S.M.A., Zhou, J., Liu, X., & Kim, T. T. (2014). An area- and power-efficient FIFO with error-reduced data compression for image/video processing. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2277-2280.||Abstract:||Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents a technique named FIFO with error-reduced data compression (FERDC) to reduce the FIFO size for various filters. The proposed FERDC significantly reduces the area and power consumption while keeping the error metrics such as mean square error (MSE) and peak signal to noise ratio (PSNR) in the acceptable range. Simulation results of a two dimensional wavelet filter shows that the proposed FERDC technique achieves the FIFO size reduction of up to 44.44% with PSNR values larger than 39 dB, which leads to the reduction of at least 31.6% in the dynamic power and 44.44% in the leakage power.||URI:||https://hdl.handle.net/10356/79393
|DOI:||10.1109/ISCAS.2014.6865625||Rights:||© 2015 Institute of Electrical and Electronics Engineers (IEEE).||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Conference Papers|
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