Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/79534
Title: | Power and area efficient clock stretching and critical path reshaping for error resilience | Authors: | Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung |
Keywords: | Better Than Worst Case Design Error Tolerance DRNTU::Engineering::Electrical and electronic engineering |
Issue Date: | 2019 | Source: | Jayakrishnan, M., Chang, A., & Kim, T. T.-H. (2019). Power and area efficient clock stretching and critical path reshaping for error resilience. Journal of Low Power Electronics and Applications, 9(1), 5-. doi:10.3390/jlpea9010005 | Series/Report no.: | Journal of Low Power Electronics and Applications | Abstract: | Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively. | URI: | https://hdl.handle.net/10356/79534 http://hdl.handle.net/10220/49055 |
ISSN: | 2079-9268 | DOI: | 10.3390/jlpea9010005 | Schools: | School of Electrical and Electronic Engineering | Organisations: | VIRTUS, IC Design Centre of Excellence | Rights: | © 2019 The Authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). | Fulltext Permission: | open | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Journal Articles |
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Power and area efficient clock stretching and critical path reshaping for error resilience.pdf | 2.92 MB | Adobe PDF | View/Open |
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