Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/79962
Title: Hybrid-mode SRAM sense amplifiers : new approach on transistor sizing
Authors: Do, Anh Tuan
Kong, Zhi Hui
Yeo, Kiat Seng
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2008
Source: Do, A. T., Kong, Z. H., Yeo, K. S. (2008). Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing. IEEE Transactions on Circuits and Systems—II. 55(10), 986-990.
Series/Report no.: IEEE transactions on circuits and systems—II
Abstract: A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It introduces a completely different way of sizing the aspect ratio of the transistors on the data-path, hence realizing a current-voltage hybrid mode Sense Amplifier. Extensive post-layout simulations have proved that the new Sense Amplifier provides both high-speed and low-power properties, with its delay and power reduced to 25.8% and 37.6% of those of the best prior art. It also offers a much better read-effectiveness and robustness against the bit- and data-line capacitances as well as VDD variations. Furthermore, the new Sense Amplifier is able to tolerate a large difference between the parasitic capacitances associated with the complementary DLs. It can operate down to a supply voltage of 0.9 V, the lowest reported for a 0.18 µm CMOS process. A modified cross-coupled amplifier is also introduced, allowing the Sense Amplifier to operate down to 0.55 V.
URI: https://hdl.handle.net/10356/79962
http://hdl.handle.net/10220/6260
ISSN: 1549-7747
DOI: 10.1109/TCSII.2008.2001965
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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