Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/79964
Title: Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing
Authors: Zhu, Ning
Goh, Wang Ling
Zhang, Weija
Yeo, Kiat Seng
Kong, Zhi Hui
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2009
Source: Zhu, N., Goh, W. L., Zhang, W., Yeo, K. S., & Kong, Z. H. (2009). Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. IEEE Transactions On Very Large Scale Integration (VLSI) Systems. pp, 1-5.
Series/Report no.: IEEE transactions on very large scale integration (VLSI) systems
Abstract: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.
URI: https://hdl.handle.net/10356/79964
http://hdl.handle.net/10220/6241
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2009.2020591
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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