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Title: Optimization of structural adders in fixed coefficient transposed direct form FIR filters
Authors: Faust, Mathias
Chang, Chip Hong
Keywords: DRNTU::Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing
Issue Date: 2009
Source: Faust, M. (2009). Optimization of structural adders in fixed coefficient transposed direct form FIR filters. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) 2009: Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore.
metadata.dc.contributor.conference: IEEE International Symposium on Circuits and Systems (2009 : Taipei, Taiwan)
Abstract: Over the last two decades, fixed coefficient FIR filters were generally optimized by minimizing the number of adders required to implement the multiplier block in the transposed direct form filter structure. In this paper, an optimization method for the structural adders in the transposed tapped delay line is proposed. Although additional registers are required, an optimal trade-off can be made such that the overall combinational logic is reduced. For a majority of taps, the delay through the structural adder is shortened except for the last tap. The one full adder delay increase for the last optimized tap is tolerable as it does not fall in the critical path in most cases. The criterion for which area reduction is possible is analytically derived and an area reduction of up to 4.5% for the structural adder block of three benchmark filters is estimated theoretically. The saving is more prominent as the number of taps grows. Actual synthesis results obtained by Synopsys Design compiler with 0.18μm TSMC CMOS libraries show a total area reduction of up to 13.13% when combined with common subexpression elimination. In all examples, up to 11.96% of the total area saved were due to the reduction of structural adder costs by our proposed method.
Schools: School of Electrical and Electronic Engineering 
Research Centres: Centre for High Performance Embedded Systems 
Rights: © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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