Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/80022
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dc.contributor.authorChen, Jiajiaen
dc.contributor.authorChang, Chip Hongen
dc.date.accessioned2010-04-14T03:57:51Zen
dc.date.accessioned2019-12-06T13:38:53Z-
dc.date.available2010-04-14T03:57:51Zen
dc.date.available2019-12-06T13:38:53Z-
dc.date.copyright2009en
dc.date.issued2009en
dc.identifier.citationChen, J., & Chang, C. H. (2009). High-level synthesis algorithm for the design of reconfigurable constant multiplier. IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, 28(12), 1844-1856.en
dc.identifier.issn0278-0070en
dc.identifier.urihttps://hdl.handle.net/10356/80022-
dc.description.abstractMultiplying a signal by a known constant is an essential operation in digital signal processing algorithms. In many application scenarios, an input or output signal is repeatedly multiplied by several predefined constants at different instances. These temporal redundancies can be exploited for the design of an efficient reconfigurable constant multiplier (RCM). An RCM achieves greater hardware savings than the conventional multiple constant multiplication architecture, limited only by the available latency of the subsystem. Motivated by a number of lucrative examples, this paper presents a new high-level design methodology for RCM. Common subexpressions in the preset constants represented in minimum signed-digit system are first eliminated to obtain a minimum depth multiroot directed acyclic graph (DAG). The DAG is converted into a primitive data flow graph (DFG) where mobile adders are identified. By scheduling each mobile adder into a control step within its legitimate time window with the minimum opportunity cost, mutually exclusive adders can be merged with significantly reduced adder and multiplexing cost. The opportunity cost for each scheduling decision is assessed by the probability displacement and disparity measures of the scheduled node as well as its predecessors and successors in the DFG. The algorithm is runtime efficient as exhaustive search for the best fusion of independently optimized constant multipliers has been avoided. Simulation results on randomly generated 12-b constant sets show that the solutions generated by the proposed algorithm are on average 19% to 25% more area–time efficient than the best reported solutions.en
dc.format.extent13 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE transactions on computer-aided design of integrated circuits and systemsen
dc.rights© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleHigh-level synthesis algorithm for the design of reconfigurable constant multiplieren
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1109/TCAD.2009.2030446en
dc.description.versionPublished versionen
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