Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/80023
Title: Area-saving technique for low-error redundant binary fixed-width multiplier implementation
Authors: Juang, Tso Bing
Wei, Chi Chung
Chang, Chip Hong
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2009
Abstract: A recently proposed architecture of redundant binary fixed-width multiplier was shown to outperform several normal binary fixed-width multipliers in terms of accuracy. However, its merit due to the carry-free addition property of the binary signed digit (BSD) partial products has been offset by the high area overhead of the redundant binary full adder tree. To achieve low–error fixed-width multiplication with smaller silicon area, we propose a hybrid structure which makes use of dual polarity high order column compressors and (3:2) counters to parallelly reduce the positive and negative BSD partial products. Our proposed technique has led to a fixed-width multiplier architecture with the same accuracy and up to 42% area saving for 10×10-bit multiplication over the conventional redundant binary fixed-width multiplier architecture in 0.18 m CMOS standard cell implementation under the same timing constraint.
URI: https://hdl.handle.net/10356/80023
http://hdl.handle.net/10220/6356
ISBN: Juang, T. B., Wei, C. C., & Chang, C. H. (2009). Area-saving technique for low-error redundant binary fixed-width multiplier implementation. International Symposium on Integrated Circuits (12th:2009:Singapore)
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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