Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/80481
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dc.contributor.authorHo, Weng-Gengen
dc.contributor.authorPammu, Ali Akbaren
dc.contributor.authorLiu, Nanen
dc.contributor.authorNe, Kyaw Zwa Lwinen
dc.contributor.authorChong, Kwen-Siongen
dc.contributor.authorGwee, Bah Hweeen
dc.date.accessioned2017-03-13T08:26:48Zen
dc.date.accessioned2019-12-06T13:50:31Z-
dc.date.available2017-03-13T08:26:48Zen
dc.date.available2019-12-06T13:50:31Z-
dc.date.issued2016en
dc.identifier.citationHo, W.-G., Pammu, A. A., Liu, N., Ne, K. Z. L., Chong, K.-S., & Gwee, B. H. (2016). Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. 2016 International Symposium on Integrated Circuits (ISIC).en
dc.identifier.urihttps://hdl.handle.net/10356/80481-
dc.description.abstractWe report a security analysis of the asynchronous-logic (async) quasi-delay-insensitive (QDI) Weak-Conditioned Half-Buffer (WCHB) cell approach against the side-channel differential power analysis (DPA) attack. When compared to the synchronous-logic (sync) standard cell approach, the WCHB cell approach is more power-balanced during the logic switching due to the unique features as follows. First, the WCHB cell approach embodies dual-rail data-encoding scheme, featuring more balanced power dissipation for different output transitions. Second, the WCHB cell approach embodies a power-constant input detector that validate the input-completeness, featuring more balanced power dissipation for different input combination. Based on 65nm CMOS process, the standard and WCHB cell approaches are simulated for 7 library cells, and compared in terms of the normalized energy deviation (NED) and normalized standard deviation (NSD). Nonetheless, the WCHB cell approach features 62% lower NED and 69% lower NSD than the standard cell approach.en
dc.description.sponsorshipASTAR (Agency for Sci., Tech. and Research, S’pore)en
dc.format.extent4 p.en
dc.language.isoenen
dc.rights© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISICIR.2016.7829712].en
dc.subjectAsynchronous logicen
dc.subjectComputer circuitsen
dc.titleSecurity analysis of asynchronous-logic QDI cell approach for differential power analysis attacken
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conference2016 International Symposium on Integrated Circuits (ISIC)en
dc.contributor.researchCentre for Integrated Circuits and Systemsen
dc.identifier.doi10.1109/ISICIR.2016.7829712en
dc.description.versionAccepted versionen
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