Please use this identifier to cite or link to this item:
Title: Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory
Authors: Aslam, Chaudhry Adnan
Guan, Yong Liang
Cai, Kui
Keywords: Microprocessors
Quantization (signal)
Threshold voltage
Computer architecture
Issue Date: 2016
Source: Aslam, C. A., Guan, Y. L., & Cai, K. (2016). Read and Write Voltage Signal Optimization for Multi-Level-Cell (MLC) NAND Flash Memory. IEEE Transactions on Communications, 64(4), 1613-1623.
Series/Report no.: IEEE Transactions on Communications
Abstract: The multi-level-cell (MLC) NAND flash channel exhibits nonstationary behavior over increasing program and erase (PE) cycles and data retention time. In this paper, an optimization scheme for adjusting the read (quantized) and write (verify) voltage levels to adapt to the nonstationary flash channel is presented. Using a model-based approach to represent the flash channel, incorporating the programming noise, random telegraph noise (RTN), data retention noise and cell-to-cell interference as major signal degradation components, the write-voltage levels are optimized by minimizing the channel error probability. Moreover, for selecting the quantization levels for the read-voltage to facilitate soft LDPC decoding, an entropy-based function is introduced by which the voltage erasure regions (error dominating regions) are controlled to produce the lowest bit/frame error probability. The proposed write and read voltage optimization schemes not only minimize the error probability throughout the operational lifetime of flash memory, but also improve the decoding convergence speed. Finally, to minimize the number of read-voltage quantization levels while ensuring LDPC decoder convergence, the extrinsic information transfer (EXIT) analysis is performed over the MLC flash channel.
ISSN: 0090-6778
DOI: 10.1109/TCOMM.2016.2533498
Schools: School of Electrical and Electronic Engineering 
Rights: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

Files in This Item:
File Description SizeFormat 
Read and write voltage signal optimization for multi-level-cell (mlc) NAND flash memory.pdf548.41 kBAdobe PDFThumbnail

Citations 10

Updated on Feb 25, 2024

Web of ScienceTM
Citations 10

Updated on Oct 25, 2023

Page view(s) 10

Updated on Feb 27, 2024

Download(s) 10

Updated on Feb 27, 2024

Google ScholarTM




Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.