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Title: A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks
Authors: Narasimman, Govind
Roy, Subhrajit
Fong, Xuanyao
Roy, Kaushik
Chang, Chip-Hong
Basu, Arindam
Keywords: STDP-Synapse
Domain wall Magnet-Synapse
Issue Date: 2016
Source: Narasimman, G., Roy, S., Fong, X., Roy, K., Chang, C.-H., & Basu, A. (2016). A Low-voltage, Low power STDP Synapse implementation using Domain-Wall Magnets for Spiking Neural Networks. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 914-917.
Abstract: Online, real-time learning in neuromorphic circuits have been implemented through variants of Spike Time Dependent Plasticity (STDP). Current implementations have used either floating-gate devices or memristors to implement such learning synapses together with non-volatile storage. However,these approaches require high voltages (≈3-12V) for weight update and entail high energy for learning (≈4-30pJ/write).We present a domain wall memory based low-voltage, low-energy STDP synapse that can operate with a power supply as low as 0.8V and update the weight at ≈40fJ/write. Device level simulations are performed to prove its feasibility. Its use in associative learning is also demonstrated by using neurons with dendritic branches to classify spike patterns from MNIST dataset.
DOI: 10.1109/ISCAS.2016.7527390
Rights: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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