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Title: Accelerating SPICE Model-Evaluation using FPGAs
Authors: Kapre, Nachiket
DeHon, André
Keywords: Analog Circuit Simulator
Spatial Computation
VLIW Scheduling
Loop Unrolling
Issue Date: 2009
Source: Kapre, N., & DeHon, A. (2009). Accelerating SPICE Model-Evaluation using FPGAs. 17th IEEE Symposium on Field Programmable Custom Computing Machines 2009, 37-44.
Conference: 17th IEEE Symposium on Field Programmable Custom Computing Machines 2009
Abstract: Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SPICE model-evaluation. Model-evaluation is a key component of the SPICE circuit simulator and it is characterized by large irregular floating-point compute graphs. We show how to exploit the parallelism available in these graphs on single-FPGA designs with a low-overhead VLIW-scheduled architecture. Our architecture uses spatial floating-point operators coupled to local high-bandwidth memories and interconnected by a time-shared network. We retime operation inputs in the model-evaluation to allow independent scheduling of computation and communication. With this approach, we demonstrate speedups of 2-18times over a dual-core 3 GHz Intel Xeon 5160 when using a Xilinx Virtex 5 LX330T for a variety of SPICE device models.
DOI: 10.1109/FCCM.2009.14
Schools: School of Computer Engineering 
Rights: © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Conference Papers

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