Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/81188
Full metadata record
DC FieldValueLanguage
dc.contributor.authorSiddharthaen
dc.contributor.authorKapre, Nachiketen
dc.date.accessioned2015-12-18T08:29:58Zen
dc.date.accessioned2019-12-06T14:23:14Z-
dc.date.available2015-12-18T08:29:58Zen
dc.date.available2019-12-06T14:23:14Z-
dc.date.issued2014en
dc.identifier.citationSiddhartha., & Kapre, N. (2014). Heterogeneous dataflow architectures for FPGA-based sparse LU factorization. 2014 24th International Conference on Field Programmable Logic and Applications (FPL), 1-4.en
dc.identifier.urihttps://hdl.handle.net/10356/81188-
dc.description.abstractFPGA-based token dataflow architectures with heterogeneous computation and communication subsystems can accelerate hard-to-parallelize, irregular computations in sparse LU factorization. We combine software pre-processing and architecture customization to fully expose and exploit the underlying heterogeneity in the factorization algorithm. We perform a one-time pre-processing of the sparse matrices in software to generate dataflow graphs that capture raw parallelism in the computation through substitution and reassociation transformations. We customize the dataflow architecture by picking the right mixture of addition and multiplication processing elements to match the observed balance in the dataflow graphs. Additionally, we modify the network-on-chip to route certain critical dependencies on a separate, faster communication channel while relegating less-critical traffic to the existing channels. Using our techniques, we show how to achieve speedups of up to 37% over existing state-of-the-art FPGA-based sparse LU factorization systems that can already run 3-4× faster than CPU-based sparse LU solvers using the same hardware constraints.en
dc.format.extent4 p.en
dc.language.isoenen
dc.rights© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FPL.2014.6927401].en
dc.subjectComputer Science and Engineeringen
dc.titleHeterogeneous dataflow architectures for FPGA-based sparse LU factorizationen
dc.typeConference Paperen
dc.contributor.schoolSchool of Computer Engineeringen
dc.contributor.conference2014 24th International Conference on Field Programmable Logic and Applications (FPL)en
dc.identifier.doi10.1109/FPL.2014.6927401en
dc.description.versionAccepted versionen
item.grantfulltextopen-
item.fulltextWith Fulltext-
Appears in Collections:SCSE Conference Papers
Files in This Item:
File Description SizeFormat 
Heterogeneous dataflow architectures for FPGA-based sparse LU factorization.pdf203.24 kBAdobe PDFThumbnail
View/Open

SCOPUSTM   
Citations 50

2
Updated on Jul 16, 2020

Page view(s)

290
Updated on Aug 12, 2022

Download(s) 50

113
Updated on Aug 12, 2022

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.