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Title: Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs
Authors: Kapre, Nachiket
DeHon, Andre
Keywords: Computer Science and Engineering
Issue Date: 2009
Source: Kapre, N., & DeHon, A. (2009). Parallelizing Sparse Matrix Solve for SPICE Circuit Simulation using FPGAs. 2009 International Conference on Field-Programmable Technology, 190-198.
Conference: 2009 International Conference on Field-Programmable Technology (FPT)
Abstract: Fine-grained dataflow processing of sparse matrix-solve computation (Ax = b) in the SPICE circuit simulator can provide an order of magnitude performance improvement on modern FPGAs. Matrix solve is the dominant component of the simulator especially for large circuits and is invoked repeatedly during the simulation, once for every iteration. We process sparse-matrix computation generated from the SPICE-oriented KLU solver in dataflow fashion across multiple spatial floating-point operators coupled to high-bandwidth on-chip memories and interconnected by a low-latency network. Using this approach, we are able to show speedups of 1.2-64x (geometric mean of 8.8x ) for a range of circuits and benchmark matrices when comparing double-precision implementations on a 250 MHz Xilinx Virtex-5 FPGA (65 nm) and an Intel Core i7 965 processor (45 nm).
DOI: 10.1109/FPT.2009.5377665
Schools: School of Computer Engineering 
Rights: © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Conference Papers

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