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Title: Spatial hardware implementation for sparse graph algorithms in GraphStep
Authors: Delorimier, Michael
Kapre, Nachiket
Mehta, Nikil
Dehon, André
Keywords: Languages
Spatial computing
Compute model
Parallel programming
Graph algorithm
Issue Date: 2011
Source: Delorimier, M., Kapre, N., Mehta, N., & Dehon, A. (2011). Spatial hardware implementation for sparse graph algorithms in GraphStep. ACM Transactions on Autonomous and Adaptive Systems, 6(3), 1-20.
Series/Report no.: ACM Transactions on Autonomous and Adaptive Systems
Abstract: How do we develop programs that are easy to express, easy to reason about, and able to achieve high performance on massively parallel machines? To address this problem, we introduce GraphStep, a domain-specific compute model that captures algorithms that act on static, irregular, sparse graphs. In GraphStep, algorithms are expressed directly without requiring the programmer to explicitly manage parallel synchronization, operation ordering, placement, or scheduling details. Problems in the sparse graph domain are usually highly concurrent and communicate along graph edges. Exposing concurrency and communication structure allows scheduling of parallel operations and management of communication that is necessary for performance on a spatial computer. We study the performance of a semantic network application, a shortest-path application, and a max-flow/min-cut application. We introduce a language syntax for GraphStep applications. The total speedup over sequential versions of the applications studied ranges from a factor of 19 to a factor of 15,000. Spatially-aware graph optimizations (e.g., node decomposition, placement and route scheduling) delivered speedups from 3 to 30 times over a spatially-oblivious mapping.
ISSN: 1556-4665
DOI: 10.1145/2019583.2019584
Rights: © 2011 Association for Computing Machinery (ACM).
Fulltext Permission: none
Fulltext Availability: No Fulltext
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