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Title: Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision Reduction
Authors: Lim, Hui Hui
Kapre, Nachiket
Issue Date: 2015
Source: Lin, H. H., & Kapre, N. (2015). Enhancing Speedups for FPGA Accelerated SPICE through Frequency Scaling and Precision Reduction. 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 163-169.
Abstract: Frequency scaling and precision reduction optimization of an FPGA accelerated SPICE circuit simulator can enhance performance by 1.5x while lowering implementation cost by 15 -- 20%. This is possible due the inherent fault tolerant capabilities of SPICE that can naturally drive simulator convergence even in presence of arithmetic errors due to frequency scaling and precision reduction. We quantify the impact of these transformations on SPICE by analyzing the resulting convergence residue and runtime. To explain the impact of our optimizations, we develop an empirical error model derived from in-situ frequency scaling experiments and build analytical models of rounding and truncation errors using Gappa-based numerical analysis. Across a range of benchmark SPICE circuits, we are able to tolerate to bit-level fault rates of 10--4 (frequency scaling) and manage up to 8-bit loss in least-significant digits (precision reduction) without compromising SPICE convergence quality while delivering speedups.
DOI: 10.1109/IPDPSW.2015.100
Rights: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
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