Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/81244
Title: Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing
Authors: Kapre, Nachiket
Chandrashekaran, Bibin
Ng, Harnhua
Teo, Kirvy
Keywords: Computer Science and Engineering
Issue Date: 2015
Source: Kapre, N., Chandrashekaran, B., Ng, H., & Teo, K. (2015). Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing. 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, 119-126.
Conference: 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Abstract: Machine learning and cloud computing techniques can help accelerate timing closure for FPGA designs without any modification to original RTL code. RTL is generally frozen closer to system delivery target to avoid injecting new unforeseen bugs or significantly affecting design characteristics. In these circumstances, developers trying to close timing are either at the mercy of random trials through placement seed exploration or through vendor-provided design space exploration tools that run a few compilation trials with changes to the CAD tool options (or parameters). Instead, we propose evaluating multiple CAD runs in parallel on the cloud, supported by a Bayesian learning and classification framework for generating multiple CAD parameter combinations most likFPGA CAD tool parametersely to help attain timing closure. We maintain a database of FPGA CAD tool parameters (input) along with associated variations in timing slack (output)to enable the learning process. A key engineering resource we use here is cheap and abundant parallelism made possible through cloud computing frameworks such as the Google Compute Engine. Across a range of open-source benchmarks, we show that learning helps improve total negative slack (TNS) scores by 10.5× (geomean) when compared to a single baseline run of Quart us 14.1 and by 7× (geomean) when compared to Alter a Quart us 14.1 Design Space Explorer (DSE).
URI: https://hdl.handle.net/10356/81244
http://hdl.handle.net/10220/39167
DOI: 10.1109/FCCM.2015.36
Schools: School of Computer Engineering 
Rights: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FCCM.2015.36].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Conference Papers

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