Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/81247
Title: System-level FPGA device driver with high-level synthesis support
Authors: Vipin, Kizheppatt
Shreejith, Shanker
Gunasekera, Dulitha
Fahmy, Suhaib A.
Kapre, Nachiket
Keywords: Computer Science and Engineering
Issue Date: 2013
Source: Vipin, K., Shreejith, S., Gunasekera, D., Fahmy, S. A., & Kapre, N. (2013). System-level FPGA device driver with high-level synthesis support. 2013 International Conference on Field-Programmable Technology (FPT), 128-135.
Conference: 2013 International Conference on Field-Programmable Technology (FPT)
Abstract: We can exploit the standardization of communication abstractions provided by modern high-level synthesis tools like Vivado HLS, Bluespec and SCORE to provide stable system interfaces between the host and PCIe-based FPGA accelerator platforms. At a high level, our FPGA driver attempts to provide CUDA-like driver behavior, and more, to FPGA programmers. On the FPGA fabric, we develop an AXI-compliant, lightweight interface switch coupled to multiple physical interfaces (PCIe, Ethernet, DRAM) to provide programmable, portable routing capability between the host and user logic on the FPGA. On the host, we adapt the RIFFA 1.0 driver to provide enhanced communication APIs along with bitstream configuration capability allowing low-latency, high-throughput communication and safe, reliable programming of user logic on the FPGA. Our driver only consumes 21% BRAMs and 14% logic overhead on a Xilinx ML605 platform or 9% BRAMs and 8% logic overhead on a Xilinx V707 board. We are able to sustain DMA transfer throughput (to DRAM) of 1.47GB/s (74% peak) of the PCIe (x4 Gen2) bandwidth, 120.2MB/s (96%) of the Ethernet (1G) bandwidth and 5.93GB/s (92.5%) of DRAM bandwidth.
URI: https://hdl.handle.net/10356/81247
http://hdl.handle.net/10220/39202
DOI: 10.1109/FPT.2013.6718342
Schools: School of Computer Engineering 
Rights: © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FPT.2013.6718342].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Conference Papers

Files in This Item:
File Description SizeFormat 
System-Level FPGA Device Driver with High-Level Synthesis Support.pdf221.39 kBAdobe PDFThumbnail
View/Open

SCOPUSTM   
Citations 20

23
Updated on May 15, 2024

Page view(s) 50

429
Updated on May 18, 2024

Download(s) 20

329
Updated on May 18, 2024

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.