Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/81247
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dc.contributor.authorVipin, Kizheppatten
dc.contributor.authorShreejith, Shankeren
dc.contributor.authorGunasekera, Dulithaen
dc.contributor.authorFahmy, Suhaib A.en
dc.contributor.authorKapre, Nachiketen
dc.date.accessioned2015-12-22T09:03:43Zen
dc.date.accessioned2019-12-06T14:26:28Z-
dc.date.available2015-12-22T09:03:43Zen
dc.date.available2019-12-06T14:26:28Z-
dc.date.issued2013en
dc.identifier.citationVipin, K., Shreejith, S., Gunasekera, D., Fahmy, S. A., & Kapre, N. (2013). System-level FPGA device driver with high-level synthesis support. 2013 International Conference on Field-Programmable Technology (FPT), 128-135.en
dc.identifier.urihttps://hdl.handle.net/10356/81247-
dc.description.abstractWe can exploit the standardization of communication abstractions provided by modern high-level synthesis tools like Vivado HLS, Bluespec and SCORE to provide stable system interfaces between the host and PCIe-based FPGA accelerator platforms. At a high level, our FPGA driver attempts to provide CUDA-like driver behavior, and more, to FPGA programmers. On the FPGA fabric, we develop an AXI-compliant, lightweight interface switch coupled to multiple physical interfaces (PCIe, Ethernet, DRAM) to provide programmable, portable routing capability between the host and user logic on the FPGA. On the host, we adapt the RIFFA 1.0 driver to provide enhanced communication APIs along with bitstream configuration capability allowing low-latency, high-throughput communication and safe, reliable programming of user logic on the FPGA. Our driver only consumes 21% BRAMs and 14% logic overhead on a Xilinx ML605 platform or 9% BRAMs and 8% logic overhead on a Xilinx V707 board. We are able to sustain DMA transfer throughput (to DRAM) of 1.47GB/s (74% peak) of the PCIe (x4 Gen2) bandwidth, 120.2MB/s (96%) of the Ethernet (1G) bandwidth and 5.93GB/s (92.5%) of DRAM bandwidth.en
dc.format.extent8 p.en
dc.language.isoenen
dc.rights© 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/FPT.2013.6718342].en
dc.subjectComputer Science and Engineeringen
dc.titleSystem-level FPGA device driver with high-level synthesis supporten
dc.typeConference Paperen
dc.contributor.schoolSchool of Computer Engineeringen
dc.contributor.conference2013 International Conference on Field-Programmable Technology (FPT)en
dc.identifier.doi10.1109/FPT.2013.6718342en
dc.description.versionAccepted versionen
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