Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/81349
Title: A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)
Authors: Zhou, Rong
Chong, Kwen-Siong
Chang, Joseph Sylvester
Gwee, Bah Hwee
Keywords: Genetic algorithm; input-complete
Null convention logic (NCL)
Input-complete
Differential cascode voltage switch logic (DCVSL)
Optimization
Quasi-delay-insensitive (QDI)
Asynchronous-logic
Issue Date: 2014
Source: Zhou, R., Chong, K.-S., Gwee, B. H., & Chang, J. S. (2014). A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(7), 989-1002.
Series/Report no.: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Abstract: In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is proposed to reduce the number of completion detection (CD) circuits while retaining the required QDI attribute. Secondly, we analyze the performance of the QDI circuits based on the proposed microcell-interleaving approach graphically in terms of power dissipation, transistor count and delay, and evaluate/determine the upper and lower boundaries of these performance profiles. Thirdly, we propose a microcell-interleaving genetic algorithm (MIGA) to stochastically optimize the proposed microcell-interleaving approach on power dissipation, transistor count, and delay. To validate the proposed design approach, a complete performance profile of ISCAS-85 C499 circuit is investigated on the basis of differential cascode voltage switch logic (DCVSL) and dynamic strong indicating (DSI) microcells. We demonstrate the efficiency of the proposed design approach by benchmarking against the competing DCVSL, null convention logic and DSI designs on five ISCAS-85 circuits. Specifically, the proposed designs, on average, are 1.77 × better in power dissipation, 1.4 × better in area, and 1.58 × better in a composite metric of power × area × delay, and reasonably slower for the lowest power dissipation points. We further demonstrate the practicality of the proposed design approach by implementing an 8-tap 16-bit asynchronous QDI finite impulse response filter. Finally, we demonstrate the ~10% and ~11% improved efficiency of the proposed MIGA over the greedy algorithm and dynamic programming, respectively.
URI: https://hdl.handle.net/10356/81349
http://hdl.handle.net/10220/39226
ISSN: 0278-0070
DOI: 10.1109/TCAD.2014.2309859
Rights: © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/TCAD.2014.2309859].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

SCOPUSTM   
Citations 20

8
Updated on Jan 13, 2023

Web of ScienceTM
Citations 20

6
Updated on Jan 24, 2023

Page view(s) 50

518
Updated on Jan 27, 2023

Download(s) 50

141
Updated on Jan 27, 2023

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.