Novel Q-factor enhancement technique for on-chip spiral inductors and its application to CMOS low-noise amplifier designs

Abstract

In this article, a novel Q-factor enhancement technique for on-chip spiral inductors is presented. Symmetric return ground structure in traditional on-chip spiral inductors is modified and shifted toward the side with stronger magnetic field caused by asymmetrical windings of inductors. In full-wave electro-magnetic simulation, it is observed that by applying this technique, inductor with higher Q-factor and larger inductance is obtained with no cost of additional chip area. Using the proposed technique, on-chip inductors are customized for a three-stage cascode low-noise amplifier (LNA) design. Fabricated in a commercial 65-nm CMOS process, the LNA features peak gain of 26.3 dB, 21.8 mW power consumption, noise figure of 5.3 dB, output P1 dB of −4 dBm, and core size of 0.15 mm2. In the comparison with prior arts, the proposed design achieves the highest gain and figure-of-merit.