Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/82156
Title: Comprehensive laser sensitivity profiling and data register bit-flips in 65 nm FPGA
Authors: He, Wei
Breier, Jakub
Bhasin, Shivam
Jap, Dirmanto
Ong, Hock Guan
Gan, Chee Lip
Keywords: Cryptographic fault attack
Laser fault injection
Issue Date: 2016
Source: He, W., Breier, J., Bhasin, S., Jap, D., Ong, H. G., & Gan, C. L. (2016). Comprehensive Laser Sensitivity Profiling and Data Register Bit-Flips for Cryptographic Fault Attacks in 65 Nm FPGA. International Conference on Security, Privacy, and Applied Cryptography Engineering, 47-65.
Abstract: FPGAs have emerged as a popular platform for security sensitive applications. As a practical attack methodology, laser based fault analyses have drawn much attention in the past years due to its superior accuracy in fault perturbation into security-critical Integrated Circuits (ICs). However, due to the insufficient device information, the practical injections work are not so efficient as expected. In this paper, we thoroughly analyze the laser fault injections to data flip-flops, instead of the widely studied configuration memory bits, of a modern nanoscale FPGA. A profiling campaign based on laser chip scan is performed on an exemplary 65 nm Virtex-5 FPGA, through the delayered silicon substrate, to identify the laser sensitivity distribution of the resource array and the fundamental logic cells. The sophisticated flip-flop bit flips are realized by launching fine-grained laser perturbations on an identified Configurable Logic Block (CLB) region. The profiled laser fault sensitivity map to FPGA resource significantly facilitate high-precision logic navigation and fault injection in practical cryptographic fault attacks. We show that the observed single- and multiple-bit faults are compatible with most proposed differential or algebraic fault analyses (DFA/AFA). Finally, further discussions on capability of reported fault models to bypass fault countermeasures like parity and dual-rail logic are also given.
URI: https://hdl.handle.net/10356/82156
http://hdl.handle.net/10220/42300
DOI: 10.1007/978-3-319-49445-6_3
Rights: © 2016 Springer International Publishing. This is the author created version of a work that has been peer reviewed and accepted for publication by International Conference on Security, Privacy, and Applied Cryptography Engineering, Springer International Publishing. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://doi.org/10.1007/978-3-319-49445-6_3].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:MSE Journal Articles
SPMS Journal Articles
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