Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/82303
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dc.contributor.authorMao, Fubingen
dc.contributor.authorChen, Yi-Chungen
dc.contributor.authorZhang, Weien
dc.contributor.authorLi, Hai (Helen)en
dc.contributor.authorHe, Bingshengen
dc.date.accessioned2016-08-26T03:07:46Zen
dc.date.accessioned2019-12-06T14:52:53Z-
dc.date.available2016-08-26T03:07:46Zen
dc.date.available2019-12-06T14:52:53Z-
dc.date.issued2015en
dc.identifier.citationMao, F., Chen, Y.-C., Zhang, W., Li, H., & He, B. (2016). Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration. ACM Transactions on Design Automation of Electronic Systems, 21(4), 1-26.en
dc.identifier.issn1084-4309en
dc.identifier.urihttps://hdl.handle.net/10356/82303-
dc.identifier.urihttp://hdl.handle.net/10220/41177en
dc.description.abstractWhile traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used modules can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time, and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this article, we propose a library-based placement and routing flow that best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in the B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 65% on average with 17% area and 8.2% delay overhead compared with the fine-grained results of Versatile Place and Route through the reuse of module information in the library for the base architecture. For other architectures, the area increase ranges from 8.32% to 25.79%, the delay varies from − 13.66% to 19.79%, and the runtime improves by 43.31% to 77.2%.en
dc.description.sponsorshipMOE (Min. of Education, S’pore)en
dc.format.extent25 p.en
dc.language.isoenen
dc.relation.ispartofseriesACM Transactions on Design Automation of Electronic Systemsen
dc.rights© 2015 ACM. This is the author created version of a work that has been peer reviewed and accepted for publication by ACM Transactions on Design Automation of Electronic Systems, ACM. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: http://dx.doi.org/10.1145/2901295.en
dc.subjectWire routingen
dc.subjectSoftware tools for EDAen
dc.titleLibrary-Based Placement and Routing in FPGAs with Support of Partial Reconfigurationen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Engineeringen
dc.identifier.doi10.1145/2901295en
dc.description.versionAccepted versionen
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