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|Title:||Design of a time-mode analog-to-digital converter utilizing a time-to-digital converter that is scalable with CMOS technology||Authors:||Teh, Jian Sen||Keywords:||Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2019||Source:||Teh, A. (2019). Design of a time-mode analog-to-digital converter utilizing a time-to-digital converter that is scalable with CMOS technology. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Aggressive scaling of CMOS technology into deep sub-micron nodes enables analog front-end circuitries to be integrated with digital back-end processors, forming System-on-Chip (SoC) solutions. However, the reduction of supply headroom available to circuits and other impairments resulting from device scaling limit the scalability of conventional front-end Analog-to-Digital converters (ADC). Time-mode ADC, comprising of a Voltage-to-Time converter (VTC) and a Time-to-Digital converter (TDC), is proposed as a solution for enabling ADCs to scale with advancing CMOS technology. Both the VTC and TDC can be realized using highly digital building blocks, circumventing the reduced supply headroom issue and benefi ting from the advantages of device scaling. This research aims to design and implement a time-mode ADC that scales with advancing CMOS technology. In the research into TDCs, two sub-blocks of TDCs are investigated. Firstly, a novel edge comparator that incorporates an input time hysteresis window of about 55 fs is proposed. This edge comparator allows a TDC to be more robust against noise and jitters in repeated measurements. Secondly, ring oscillators employing the negative skewed delay scheme are analyzed to understand the mechanism behind this scheme. Therefore, an optimum con figuration of negative skewed ring oscillator can be chosen for the TDC implementation. Both the proposed edge comparator and the analysis of negative skewed ring oscillators are verified using prototype chips fabricated in a standard 0.18 μm CMOS technology. In addition, a novel branching TDC architecture is proposed. The branching technique interpolates between the phases of a core ring oscillator used by the TDC. Hence, the TDC time resolution can be finer than the tap-to-tap delay of the ring oscillator. The branching technique allows two phase interpolation methods to be realized. Namely, through deterministic or stochastic positioning of the interpolating edges. The former and latter methods are demonstrated by a 12-bit branching TDC prototype chip fabricated in a standard 40 nm CMOS technology, and a 14-bit fully synthesizable stochastic-based branching TDC simulation in a standard 65 nm CMOS technology, respectively. The former and latter TDCs achieve interpolation factors of 4 and 85.3, respectively. Finally, an 8-bit highly digital time-mode ADC is proposed. It comprises of a novel voltage-controlled oscillator (VCO)-based VTC with time interval amplification capability and a stochastic-based branching TDC. The proposed time-mode ADC accepts rail-to-rail inputs, not limited by the reduced supply headroom issue. It also does not require any voltage references or amplifiers. Hence, it is able to scale well with advancing CMOS technology. The proposed time-mode ADC is verified using prototype chip fabricated in a standard 40 nm CMOS technology. At a sampling rate of 15 MS/s, it achieves a signal-to-noise and distortion ratio (SNDR) of 39.9 dB and a Walden figure of merit of 464 fJ/conv.-step.||URI:||https://hdl.handle.net/10356/82865
|DOI:||10.32657/10356/82865||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Jun 25, 2022
Updated on Jun 25, 2022
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