Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/82889
Full metadata record
DC FieldValueLanguage
dc.contributor.authorLee, Kwang Hongen
dc.contributor.authorBao, Shuyuen
dc.contributor.authorZhang, Lien
dc.contributor.authorKohen, Daviden
dc.contributor.authorFitzgerald, Eugeneen
dc.contributor.authorTan, Chuan Sengen
dc.date.accessioned2017-05-03T07:42:23Zen
dc.date.accessioned2019-12-06T15:07:38Z-
dc.date.available2017-05-03T07:42:23Zen
dc.date.available2019-12-06T15:07:38Z-
dc.date.issued2016en
dc.identifier.citationLee, K. H., Bao, S., Zhang, L., Kohen, D., Fitzgerald, E., & Tan, C. S. (2016). Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process. Applied Physics Express, 9(8), 086501-.en
dc.identifier.issn1882-0778en
dc.identifier.urihttps://hdl.handle.net/10356/82889-
dc.description.abstractThe integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform.en
dc.description.sponsorshipNRF (Natl Research Foundation, S’pore)en
dc.format.extent14 p.en
dc.language.isoenen
dc.relation.ispartofseriesApplied Physics Expressen
dc.rights© 2016 The Japan Society of Applied Physics. This is the author created version of a work that has been peer reviewed and accepted for publication by Applied Physics Express, The Japan Society of Applied Physics. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.7567/APEX.9.086501].en
dc.subjectCMOS integrated circuitsen
dc.subjectGallium arsenideen
dc.titleIntegration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer processen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.7567/APEX.9.086501en
dc.description.versionAccepted versionen
item.fulltextWith Fulltext-
item.grantfulltextopen-
Appears in Collections:EEE Journal Articles
Files in This Item:
File Description SizeFormat 
Integration of GaAs, GaN and Si-CMOS on a common 200.pdf560.17 kBAdobe PDFThumbnail
View/Open

SCOPUSTM   
Citations 10

29
Updated on Mar 10, 2021

PublonsTM
Citations 10

27
Updated on Mar 10, 2021

Page view(s) 50

367
Updated on Jul 5, 2022

Download(s) 20

223
Updated on Jul 5, 2022

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.