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Title: Triplet spike time dependent plasticity in a floating-gate synapse
Authors: Gopalakrishnan, Roshan
Basu, Arindam
Keywords: SNN
Floating gate
Long term potentiation
Long term depression
Spike triplet
Computational neuroscience
Issue Date: 2015
Source: Gopalakrishnan, R., & Basu, A. (2015). Triplet spike time dependent plasticity in a floating-gate synapse. 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 710-713.
Conference: 2015 IEEE International Symposium on Circuits and Systems (ISCAS)
Abstract: Synapses plays an important role of learning in a neural network; the learning rules which modify the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP). This paper describes the compact implementation of a synapse using single floating-gate (FG) transistor (and two additional high voltage transistors) that can store a weight in a non-volatile manner and demonstrate the triplet STDP (T-STDP) learning rule developed to explain biologically observed plasticity. We describe a mathematical procedure to obtain control voltages for the FG device for T-STDP and also show measurement results, from a FG synapse fabricated in TSMC 0.35μm CMOS process to support the theory.
DOI: 10.1109/ISCAS.2015.7168732
Schools: School of Electrical and Electronic Engineering 
Rights: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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