Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/83419
Title: Exploiting FPGA Block Memories for Protected Cryptographic Implementations
Authors: Bhasin, Shivam
Danger, Jean-Luc
Guilley, Sylvain
He, Wei
Keywords: FPGA
Side-Channel Analysis
Issue Date: 2015
Source: Bhasin, S., Danger, J.-L., Guilley, S., & He, W. (2015). Exploiting FPGA Block Memories for Protected Cryptographic Implementations. ACM Transactions on Reconfigurable Technology and Systems, 8(3), 1-16.
Series/Report no.: ACM Transactions on Reconfigurable Technology and Systems
Abstract: Modern field programmable gate arrays (FPGAs) are power packed with features to facilitate designers. Availability of features like large block memory (BRAM), digital signal processing cores, and embedded CPU makes the design strategy of FPGAs quite different from ASICs. FPGAs are also widely used in security-critical applications where protection against known attacks is of prime importance. We focus on physical attacks that target physical implementations. To design countermeasures against such attacks, the strategy for FPGA designers should be different from that in ASIC. The available features should be exploited to design compact and strong countermeasures. In this article, we propose methods to exploit the BRAMs in FPGAs for designing compact countermeasures. Internal BRAM can be used to optimize intrinsic countermeasures such as masking and dual-rail logics, which otherwise have significant overhead (at least 2 × ) compared to unprotected ones. The optimizations are applied on a real AES-128 co-processor and tested for area overhead and resistance on Xilinx Virtex-5 chips. The presented masking countermeasure has an overhead of only 16% when applied on AES. Moreover, the dual-rail precharge logic (DPL) countermeasure has been optimized to pack the whole sequential part in the BRAM, hence enhancing the security. Proper robustness evaluations are conducted to analyze the optimization in terms of area and security.
URI: https://hdl.handle.net/10356/83419
http://hdl.handle.net/10220/41430
ISSN: 1936-7406
DOI: 10.1145/2629552
Rights: © 2015 Association for Computing Machinery (ACM). This is the author created version of a work that has been peer reviewed and accepted for publication by ACM Transactions on Reconfigurable Technology and Systems, Association for Computing Machinery (ACM). It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1145/2629552].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:TL Journal Articles

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